عباس عبد الامير جاسم

This paper proposes a new hardware design for image cryptographic system, based on Henon chaotic map and implemented on FPGA (Field Programmable Gate Array) platform. Xilinx System Generator tool with MATLAB Simulink and Vivado design suite are employed to implement the hardware design inside xc7a100tcsg324-1 FPGA chip. The Henon chaotic map, is utilized to generate pseudorandom addresses that used to permute the pixels' positions of plain - gray and RGB - images to obtain encrypted images which stored in block RAM inside the FPGA. The encrypted image will be read from the block RAM and sent to the target receiver. The mean goal of this work is to accelerate the processing of image encryption and decryption. The crypto-system performance is evaluated using MSE (Mean Square Error) and CCA Correlation Coefficient Analysis. The results demonstrate that the proposed hardware design achieves high speed processing as compared to software encryption/decryption programs. The proposed hardware system is faster than the software version for multiple images sizes. It achieved speedup factor equals 279.5 for 128x128 image, 70.8 for 256x256 image, 23.7 for 512x512 image and 10.8 for 1024x1024 images. © 2025 IEEE.